EDN

Hardened Floating-Point DSP Blocks

Altera Corporation changed the game as it relates to floating-point DSP performance in an FPGA. Altera is the first programmable logic company to integrate hardened IEEE 754-compliant, floating-point ...
EDN

Implementing floating-point DSP on FPGAs

For developers using FPGAs for the implementation of floating-point DSP functions, one key challenge is how to decompose the computation algorithm into sequences of parallel hardware processes while ...
CIOL

Altera changes game for floating point DSP in FPGAs

SAN JOSE, USA: Altera Corp. changed the game as it relates to floating-point DSP performance in an FPGA. Altera is the first programmable logic company to integrate hardened IEEE 754-compliant, ...
Phys.org

TI ADDS FLOATING-POINT DSP TO ROADMAP AND EXTENDS PRICE/PERFORMANCE BY MORE THAN 3X

HOUSTON (July 19, 2004) - DSP-based system designers can improve system performance while decreasing DSP costs by using the new TMS320C6711 digital signal processor (DSP) announced today from Texas ...
Electronics Weekly

Xilinx supports floating-point DSP in 7 Series FPGAs

Xilinx has announced the availability of ISE Design Suite 13.3 featuring new capabilities for DSP designers to implement bit-accurate single, double and full custom precision floating-point math ...
Electronics Weekly

ADI puts floating point Sharc DSP into the embedded mainstream

Analog Devices (ADI) has introduced a multi-core Sharc DSP device which it believes will remove the power limitations of using floating point DSP for highly determinisitic audio processing. As a ...
Design-Reuse

Altera Demonstrates Industry's First Model-Based Floating-Point DSP Capabilities for FPGAs

Altera's New Highly-Efficient Floating-Point DSP Design Flow Validated by BDTI, Industry's Most Trusted Source of Independent DSP Technology Analysis San Jose, Calif., September 12, 2011—Altera ...
Electronic Design

As Audio Apps Push the Quality Frontier, Floating-Point DSP Architectures Take Center Stage

The shift to larger data words and higher sampling rates in audio applications is creating challenges for the audio developer. Here’s some advice on how to deal with the transition. The demand for ...
New Electronics

Cadence Tensilica FloatingPoint DSP family targets compute-intensive applications

Cadence Design Systems has unveiled the Tensilica FloatingPoint DSP family, which has been designed to provide a scalable and configurable solution specifically for floating-point-centric workloads.
CIOL

CEVA intros vector floating-point DSP core

MESA, USA: Addressing the wireless infrastructure modem chip market, rather than the handset chip market, CEVA has introduced the CEVA XC4500 DSP core, which they claim to be "the world's first vector ...
Design-Reuse

Altera Changes the Game for Floating Point DSP in FPGAs

San Jose, Calif., April 22, 2014– Altera Corporation (Nasdaq: ALTR) today changed the game as it relates to floating-point DSP performance in an FPGA. Altera is the first programmable logic company to ...